1. Technical Field
The present invention relates generally to integrated circuit design, and more particularly, to determination of a probability of fault (POF) function with critical defect size maps.
2. Related Art
The “critical area” of a very large scale integrated (VLSI) circuit layout is a measure that reflects the sensitivity of the layout to defects occurring during the manufacturing process. Critical area is widely used to predict the yield of a VLSI chip. Yield prediction is essential in today's VLSI manufacturing due to the growing need to control cost. Models for yield estimation are based on the concept of critical area which represents the main computational problem in the analysis of yield loss due to spot defects during fabrication. Spot defects are caused by particles such as dust and other contaminants in materials and equipment and are classified into two types: First, “extra material” defects cause shorts between different conducting regions by causing shapes to print slightly larger as a consequence of the manufacturing process. Second, “missing material” defects create open circuits by causing shapes to print slightly smaller as a consequence of the manufacturing process. Extra material defects are the ones that appear most frequently in a typical manufacturing process and are the main reason for yield loss.
A parameter that is, in certain approaches, used to determine critical area and is also useful in evaluating an IC design relative to defects is a probability of fault (POF) function. A POF function is a measure of the probability that a random defect of a given size r landing on the IC design will cause an electrical fault in the circuit. The POF function is dependent on the IC design, and is also useful for determining random defect failure probabilities for various manufacturing process models. The POF function can also be used to analyze characteristics of an IC design as it relates to defect sensitivity. Another useful parameter is a defect density function, which is a measure of the probability that a random defect of a particular size r will occur on the chip, independent of the chip design. The POF function for a particular design is independent of the defect density function. The probability that a random defect will occur on an IC design and cause an electrical fault (e.g., short, wire breaks (opens), or via blockage) is given by:
  Θ  =            CriticalArea              Area        ⁢                                  ⁢        OfLayout              =                  ∫        0        ∞            ⁢                        POF          ⁡                      (            r            )                          ⁢                  DefectDensity          ⁢                                          (          r          )                ⁢                  ⅆ          r                    
Currently, there are two methods of determining critical area: a Monte Carlo approach and a critical defect size mapping approach. In the Monte Carlo approach, critical area is approximated by randomly simulating defects on the actual layout having varying sizes. In this approach, the POF function is based on statistical data, and is used to perform integration with the defect density function to determine the critical area. One problem with the Monte Carlo approach, however, is that it uses a gross approximation of the POF function, which significantly lowers accuracy of the critical area determination. In addition, run-times for a Monte Carlo analysis are an order of magnitude greater than the critical defect size mapping approach. The critical defect size mapping approach constructs a critical defect size map in the form of a Voronoi diagram based on the layout geometry, which can be used to compute an exact critical area rather than an approximation. A shortcoming of the conventional critical defect size mapping (Voronoi) approach, however, is that the POF function is not determined.
In view of the foregoing, there is a need in the art for determining a probability of fault function using a critical defect size mapping (e.g., Voronoi) approach.